VLSI: Winning Competitions

In my previous post I explained an ad hoc competition I tried to start between me and my colleagues for my VLSI class. It worked and I ended up pulling a few people into the "competition". The rules were as follows: Smallest total area for the functional 32bit adder or 16bit if they were undergrad students. The implementation of the PPA adder everyone created, not the ripple carry that was also created for the project, was to be sized. The ruleset used must be the TSMC .035 ruleset.

So clearly the undergrad had an advantage (technically i was undergrad, but i was working with a grad student so our project had to be 32bits) but I was pretty sure my sizing practices would get me the win. Also I was the only one using 45 degree angles to help with routing at the time. This would later cause some neat looking designs.

Anyway, me and my partner (Nate Prosser) came up with a Brent-Kung PPA Adder that measured in at: 436x3584 Lambda.

Above you see the 32bit Brent Kung PPA Adder that I laid out (Partner figured out all the logic). Really that was a last minute attempt at design as we had switched over from a Carry Look Ahead type adder to a PPA. We decided to switch about a week before the project due date, whoops. So we designed and laid out the 32bit BK PPA in just about a week. Long nights in the lab were how it was completed. Infact I spent about 24 hours in the lab trying to lay this out (that was 2 weeks after I gave up caffeine).

A large project like this does not just happen in one go, you start small and build up with modules. In a size competition you optimize the small blocks first, and luckily I had spent the middle part of the term making really small layouts for the basic blocks I would later use. These included Inverters, Dual-Inverters, Buffers, XORs of multiple length, ANDs, ORs, 1 Bit Adders, etc... That allowed me to finish my layout in the week we had left.

This project included 3 basic modules: 2 bit XORs for the output logic, a propogate/generate generator (we could have chosen a better name I guess) and a Dot Operator.



The Dot Operator measured in at 58x105 Lambda. And good luck trying to figure out the logic from these pictures. If you're really interested ask me for the transistor level schematics.




The propogate/generate generator measured in at 68x112 Lambda. While this may look like it wastes space, the large metal rails are there for a reason. They carry the power for all those transistors (VDD on top, GND on bottom).



The 2 input XORs used on the output of the BK PPA Adder measured in at 50x87 Lambda. The set of nfets and pfets on the far left of the XOR is a dual inverter, a way I combined two inverters into one substrate that became so popular in my class everyone was using them. Really I shouldn't have been sharing my secrets for the sake of winning but I wanted it to be a decent competition. Also you get to see some of the 45 degree poly action in this XOR version.

Throughout the final layout of the project (Wednesday and Thursday night before the project was due) routing metal connections was the most frustrating part of the project. Somehow I figured out the routing and as you can see in my two example pictures it got pretty hectic. But its over and we got an A on the project regardless of my horribly thought out final implementation. I still have to get other group's numbers so I can see who won.

Also I would like to mention that our class lost its happiest member that final project week. Seth Policzer died in a house fire on the last Thursday night (Friday morning November 9th 2007) of the class. I was in the lab for 24 hours that night and I remember seeing him at about 7:30pm in the lab working with Jesse Harvey. He was leaving to eat a meal his roommates had spent all day preparing. I remember saying "see you tomorrow" to him only to fall short of that promise. I'll miss you Seth, you really were the happiest person in that class.