VLSI: Competing for the Smallest Hardware

A little context: I am a Computer Engineering student at RIT (Rochester Inst. of Tech.). I am currently (Fall '07) in a VLSI (Very Large Scale Integration) class, which teaches me how to do physical layouts of transistors to put logic on chips. However, I am a very lazy person when it comes to doing homework. Added to that I am a pretty competitive person and try and make competitions out of a lot of things. Normally I wouldn't go to the lengths I do in a class like this, but I am competing with my colleagues.

They don't acknowledge the competition I so fiercely attack. They claim they're not competing with me, as they did not know about it in the beginning. That is a cop out in my world, they're just trying to make me lose my edge.

So far, I'm winning. I judge everything by smallest area and correct behavior of the circuit. This requires some LVS (Layout vs Schematic) and basic measurements done in the program. A note: We're all using the same technology process (which is: rules and basic sizes of certain things in the layouts) so you cannot win by using a smaller process (ie 45nm vs 350nm). In this case we're using the TSMC035 process.

Lets get down to the goodies. My only screenshot at the moment. My 1 bit mirror adder, which was the smallest in the class (from a decently large survey I made).

This beaut measures in at 107x160lambda. Really it is pretty large, but it was easy to make. Any other 1 bit adder could be made much smaller than that. However, the nice thing about Mirror adders, as you can see, is the NFETs and PFETs have the same inputs (see the poly layer: red) in the same places and the widths are proportional in the same area.

More competing to come later. I'm currently working on a 32bit Carry Look Ahead adder for our final project (which will be significantly bigger than a 1 bit mirror adder).